In recent years, with advancement of digital technologies of electronic hardware, semiconductor memory devices which have a large capacity and are nonvolatile have been developed vigorously to store data of music, image, information and so on. Among the nonvolatile semiconductor memory devices, for example, a nonvolatile semiconductor memory device using a ferroelectric as a capacitive element has been already used in many fields. In addition to the nonvolatile semiconductor memory device (hereinafter referred to as FeRAM) using such a ferroelectric capacitor, a nonvolatile semiconductor memory device (hereinafter referred to as MRAM) which retains a changed resistance value by utilizing a tunneling magnetic resistive effect, and a nonvolatile semiconductor memory device (hereinafter referred to as ReRAM) using a material which is adapted to change a resistance value in response to electric pulses applied and retains the changed resistance value, have attracted an attention. The MRAM and the ReRAM also have attracted an attention because of its high compatibility with a standard Si semiconductor process step.
In the nonvolatile semiconductor memory device, memory cell holes are typically formed at cross points where word lines cross bit lines, respectively, memory elements and cell select elements such as diodes which are connected in series with the memory elements are arranged inside the memory cell holes, respectively, and memory cells each of which is composed of the memory element and the cell select element are integrated in matrix. In addition, a peripheral circuit is provided adjacently to the memory cells arranged in matrix to drive the memory cells to process data from the memory cells, etc. Depending on a wiring structure of wires for connecting lead-out wires connected to memory cells to wires in the peripheral circuit, high-dense integration of the nonvolatile semiconductor memory device is impeded.
To solve this problem and implement a nonvolatile semiconductor memory device which is highly integrated, for example, a structure of a cross-point MRAM is proposed, in which memory cells each consisting of a TMR (tunneling magneto-resistive) element and a cell select diode which are connected in series are arranged in matrix (see e.g., patent document 1). Lead-out wires connected to memory cells are electrically connected to a peripheral circuit which is disposed above and adjacently to the memory cells.
As in the above MRAM, a structure of a cross-point FeRAM is proposed, in which lead-out wires connected to memory cells are led out to the upper side and electrically connected to an adjacent peripheral circuit (see e.g., patent document 2). Furthermore, it is proposed that, to reduce a chip area, localized wires are formed to connect a ferroelectric capacitor array region and a transistor formed right below the ferroelectric capacitor array region to a peripheral circuit, in the cross-point FeRAM (see e.g., patent document 3).
In an example of a cross-point ReRAM, memory plugs each of which has seven layers are formed at cross points between X-direction conductive array lines and Y-direction conductive array lines, and a memory element including a composite metal oxide sandwiched between two electrode layers, a non-ohmic element which is formed on the memory element and has a metal-insulator-metal (MIM) structure, and an electrode layer are stacked together inside each memory plug (e.g., see Patent Document 4). Electric connections or wires between the memory plug including the memory element and non-ohmic element, and a drive circuit such as a transistor or an adjacent peripheral circuit are not disclosed. It is presumed that these wires are formed in a process step performed separately.    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2004-193282    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-363124    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2004-356313    Patent document 4: U.S. Pat. No. 6,753,561 Specification